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sci-electronics/yosys

framework for Verilog RTL synthesis

Screenshots

  • yosys-9999

    View      Download      Browse     License: ISC   
    Overlay: salfter
  • yosys-0.47
    amd64

    View      Download      Browse     License: ISC   
    Overlay: salfter
  • yosys-0.40-r1
    ~amd64

    View      Download      Browse     License: ISC   
    Overlay: guru
  • yosys-0.40
    ~amd64

    View      Download      Browse     License: ISC   
    Overlay: vowstar
  • yosys-0.32
    ~amd64

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    Overlay: vowstar
  • yosys-0.19
    ~amd64
    tcl libffi readline libedit zlib test

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    Overlay: qsx
  • yosys-0.9.3981
    ~amd64 ~x86
    +abc clang libffi libedit readline python python_single_target_python3_8 python_single_target_python3_9 python_single_target_python3_10 python_single_target_python3_11

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    Overlay: xdch47

USE Flags

tcl
Global: Adds support the Tcl language
libffi
Global: use dev-libs/libffi to call native methods
readline
Global: Enables support for libreadline, a GNU line-editing library that almost everyone wants
libedit
Global: Use the libedit library (replacement for readline)
zlib
Global: Adds support for zlib (de)compression
test
Global: Workaround to pull in packages needed to run with FEATURES=test. Portage-2.1.2 handles this internally, so don't set it in make.conf/package.use anymore
+abc
* This flag is undocumented *
clang
* This flag is undocumented *
python
Global: Adds support/bindings for the Python language
python_single_target_python3_8
* This flag is undocumented *
python_single_target_python3_9
* This flag is undocumented *
python_single_target_python3_10
* This flag is undocumented *
python_single_target_python3_11
* This flag is undocumented *