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sci-electronics/yosys

framework for Verilog RTL synthesis

Screenshots

  • yosys-9999

    View      Download      Browse     License: ISC   
    Overlay: salfter
  • yosys-0.48
    amd64

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    Overlay: salfter
  • yosys-0.47
    ~amd64 ~x86
    +abc clang +libffi +libedit readline python python_single_target_python3_10 python_single_target_python3_11 python_single_target_python3_12

    View      Download      Browse     License: ISC   
    Overlay: xdch47
  • yosys-0.40-r1
    ~amd64

    View      Download      Browse     License: ISC   
    Overlay: guru
  • yosys-0.40
    ~amd64

    View      Download      Browse     License: ISC   
    Overlay: vowstar
  • yosys-0.32
    ~amd64

    View      Download      Browse     License: ISC   
    Overlay: vowstar
  • yosys-0.19
    ~amd64
    tcl libffi readline libedit zlib test

    View      Download      Browse     License: ISC   
    Overlay: qsx
  • yosys-0.9.3981
    ~amd64 ~x86
    +abc clang libffi libedit readline python python_single_target_python3_8 python_single_target_python3_9 python_single_target_python3_10 python_single_target_python3_11

    View      Download      Browse     License: ISC   
    Overlay: xdch47

ChangeLog

commit 9f113f9ff5f19f3ec0e1b3c45961baa1a87bf1b0
Author: Felix Neumärker <xdch47@posteo.de>
Date: Fri Nov 29 20:54:21 2024 +0100

yosys: update

commit 05c949c22e2a7c3f89194dab01a92f6f6ae9e040
Author: Felix Neumärker <xdch47@posteo.de>
Date: Fri Nov 29 18:45:37 2024 +0100

yosys import

commit b15ed6f68dbe7bbda8908dd4894926fc09beec4b
Author: Felix Neumärker <xdch47@posteo.de>
Date: Thu Jul 7 12:55:48 2022 +0200

sci-electronics/yosys:

Package-Manager: Portage-3.0.30, Repoman-3.0.3
Signed-off-by: Felix Neumärker <xdch47@posteo.de>

commit c24657ed0d269e65632550f0c84d97dcb7bb23b3
Author: Felix Neumärker <xdch47@posteo.de>
Date: Sun Jan 31 23:22:20 2021 +0100

sci-electronics/yosys: add package

Package-Manager: Portage-3.0.14, Repoman-3.0.2
Signed-off-by: Felix Neumärker <xdch47@posteo.de>